DESCRIPTION OF THE PRIOR ART
APS are solid state imagers wherein each pixel typically contains a photo-sensing means, reset means, a charge transfer means, a charge to voltage conversion means, and all of part of an amplifier. Prior art APS devices have been operated in a manner where each line, or row, of the imager is selected and then read out using a column select signal (analogous to the selection and reading of a memory device). In prior art devices the connection, or contact, to the various nodes within the pixels of a given row is accomplished on a per pixel basis. This is true even though the pixels exist on the same electrical node within a row (see FIG. 1). Since these contact regions are placed in each pixel, and contact regions typically consume a large amount of pixel area due to the overlap of metal layers required, inclusion of these contact regions in each pixel reduces the fill factor for the pixel because it takes up area that could otherwise be used for the photodetector. This reduces the sensitivity and saturation signal of the sensor. This adversely affects the photographic speed and dynamic range of the sensor, performance measures that are critical to obtaining good image quality. In addition prior art APS pixels have included the entire amplifier, address and reset transistors within a single pixel, and have made operative interconnection of these components and the photodetector entirely within a single pixel boundary. This leads to inefficiencies of layout and produces pixels with small fill factors.
In order to build high resolution, small pixel APS devices, it is necessary to use sub-.mu.m CMOS processes in order to minimize the area of the pixel allocated to the row select transistor and other parts of the amplifier in the pixel. In essence, it takes a more technologically advanced and more costly process to realize the same resolution and sensitivity in an APS device as compared to a standard charge coupled device (CCD) sensor. However, APS devices have the advantages of single 5V supply operation, lower power consumption, x-y addressability, image windowing, and the ability to effectively integrate signal processing electronics on-chip, when compared to CCD sensors.
A typical prior art APS pixel 10 is shown in FIG. 1. The pixel comprises a photodetector (PDET) 11, that can be either a photodiode or photogate, a transfer gate (TG) 12, floating diffusion (FD) 14, reset transistor with a reset gate (RG) 16, row select transistor with a row select gate (RSG) 4, and signal transistor (SIG) 5. Note that all of the electrical components required to readout and address the pixel are contained entirely within a single pixel boundary, and are operatively connected entirely within a single pixel boundary. Regions to provide contact to each of the various electrical nodes within the pixel that are common to a row are designated in FIG. 1 and shown schematically in FIG. 2. These are Transfer Gate Contact (TGC) 13, Reset Gate Contact (RGC) 17, and Row Select Gate Contact (RSGC) 3. Additionally there are contact regions that are common to a column. These are also shown in FIGS. 1 and 2. These are power supply contacts (VDDC) 9 and the pixel output node contact (OUTC) 8. Note that there are separate and individual contact regions in each pixel even though some are common to a row or column. It is evident that the area consumed by these contact regions is a significant portion of the pixel area, thus limiting the area available for the photodetector, which reduces the fill factor and sensitivity of the pixel.
It should be apparent, from the foregoing discussion, that there remains a need in the art for APS sensors that have increased fill factors. This and other problems are addressed by the present invention.